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PRELIMINARY
CY7C1330AV25 CY7C1332AV25
18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write
Features
* Fast clock speed: 250, 200 MHz * Fast access time: 2.0, 2.25 ns * Synchronous Pipelined Operation with Self-timed Late Write * Internally synchronized registered outputs eliminate the need to control OE * 2.5V core supply voltage * 1.4-1.9V VDDQ supply with VREF of 0.68-0.95V -- Wide range HSTL I/O Levels * Single Differential HSTL clock Input K and K * Single WE (READ/WRITE) control pin * Individual byte write (BWS[a:d]) control (may be tied LOW) * Common I/O * Asynchronous Output Enable Input * Programmable Impedance Output Drivers * JTAG boundary scan for BGA packaging version * Available in a 119-ball BGA package (CY7C1330AV25 and CY7C1332AV25)
Functional Description
The CY7C1330AV25 and CY7C1332AV25 are high performance, Synchronous Pipelined SRAMs designed with late write operation. These SRAMs can achieve speeds up to 250 MHz. Each memory cell consists of six transistors. Late write feature avoids an idle cycle required during the turnaround of the bus from a read to a write. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (K). The synchronous inputs include all addresses (A), all data inputs (DQ[a:d]), Chip Enable (CE), Byte Write Selects (BWS[a:d]), and read-write control (WE). Read or Write Operations can be initiated with the chip enable pin (CE). This signal allows the user to select/deselect the device when desired. Power down feature is accomplished by pulling the Synchronous signal ZZ HIGH. Output Enable (OE) is an asynchronous input signal. OE can be used to disable the outputs at any given time. Four pins are used to implement JTAG test capabilities. The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation.
Configuration
CY7C1330AV25 - 512K x 36 CY7C1332AV25 - 1M x 18
Logic Block Diagram
K,K
Clock Buffer
D Data-In REG. CE Q (2stage)
OUTOUT REGISTERS and LOGIC
Ax CE CONTROL and WRITE LOGIC 512Kx36 1Mx18
DQx
WE BWSx
MEMORY ARRAY
ZZ
OE
AX
DQX
BWSX
512Kx36 X = 18:0 X = a, b, c, d X = a, b, c, d 1Mx18
X = 19:0 X = a, b X = a, b
Cypress Semiconductor Corporation Document No: 001-07844 Rev. *A
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised September 20, 2006
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PRELIMINARY
Selection Guide
CY7C1330AV25-250 CY7C1332AV25-250 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.0 600 280
CY7C1330AV25 CY7C1332AV25
CY7C1330AV25-200 CY7C1332AV25- 200 2.25 550 260
Unit ns mA mA
Pin Configurations 119-Ball BGA (14 x 22 x 2.4 mm)
CY7C1330AV25 (512K x 36)
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ
2
A A A DQc DQc DQc DQc DQc VDD
DQd
3
A A A VSS VSS VSS BWSc VSS VREF VSS BWSd VSS VSS VSS M1 A TDI
4
NC NC VDD ZQ CE OE NC NC VDD K K WE A0 A1 VDD A TCK
5
A A A VSS VSS VSS BWSb VSS VREF VSS BWSa VSS VSS VSS M2 A TDO
6
A A A DQb DQb DQb DQb DQb VDD DQa DQa DQa DQa DQa A NC NC
7
VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ
DQd DQd DQd DQd A NC TMS
CY7C1332AV25 (1M x 18)
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQb NC VDDQ NC DQb VDDQ NC DQb VDDQ DQb NC NC NC VDDQ
2
A A A NC DQb NC DQb NC VDD
DQb
3
A A A VSS VSS VSS BWSb VSS VREF VSS NC VSS VSS VSS M1 A TDI
4
NC NC VDD ZQ CE OE NC NC VDD K K WE A0 A1 VDD NC TCK
5
A A A VSS VSS VSS NC VSS VREF VSS BWSa VSS VSS VSS M2 A TDO
6
A A A DQa NC DQa NC DQa VDD NC DQa NC DQa NC A A NC
7
VDDQ NC NC NC DQa VDDQ DQa NC VDDQ DQa NC VDDQ NC DQa NC ZZ VDDQ
NC DQb NC DQb A A TMS
Document No: 001-07844 Rev. *A
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PRELIMINARY
Pin Definitions
Name A BWSa BWSb BWSc BWSd WE K,K CE OE I/O Type InputSynchronous InputSynchronous Description
CY7C1330AV25 CY7C1332AV25
Address Inputs used to select one of the address locations. Sampled at the rising edge of the K. Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BWSa controls DQa, BWSb controls DQb, BWSc controls DQc, BWSd controls DQd. Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to initiate a write sequence and high to initiate a read sequence. Clock Inputs. Used to capture all synchronous inputs to the device. Chip Enable Input, active LOW. Sampled on the rising edge of CLK. Used to select/deselect the device. Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A[x:0] during the previous clock rise of the read cycle. The direction of the pins is controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave as outputs. When HIGH, DQa-DQd are placed in a tri-state condition. The outputs are automatically tri-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE. DQ a,b,c,d are 9 bits wide Mode control pins, used to set the proper read protocol. For specified device operation, M1 must be connected to VSS, and M2 must be connected to VDD or VDDQ. These mode pins must be set at power-up and cannot be changed during device operation. ZZ "sleep" Input. This active HIGH input places the device in a non-time critical "sleep" condition with data integrity preserved. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. Power supply inputs to the core of the device. For this device, the VDD is 2.5V. Power supply for the I/O circuitry. For this device, the VDDQ is 1.5V. Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs as well as AC measurement points. Ground for the device. Should be connected to ground of the system. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK. Serial clock to the JTAG circuit. No connects.
InputSynchronous InputDifferential Clock InputSynchronous InputAsynchronous
DQa DQb DQc DQd
I/OSynchronous
M1, M2
Read Protocol Mode Pins
ZZ ZQ
InputAsynchronous Input
VDD VDDQ VREF VSS TDO TDI TMS TCK NC
Power Supply I/O Power Supply InputReference Voltage Ground JTAG serial output Synchronous JTAG serial input Synchronous Test Mode Select Synchronous JTAG serial clock -
Document No: 001-07844 Rev. *A
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PRELIMINARY
Introduction
Functional Overview The CY7C1330AV25 and CY7C1332AV25 are synchronouspipelined Late Write SRAMs running at speeds up to 250 MHz. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 2.0 ns (250-MHz device). Accesses can be initiated by asserting Chip Enable (CE) on the rising edge of the clock. The address presented to the device will be latched on this edge of the clock. The access can either be a read or write operation, depending on the status of the Write Enable (WE). BWS[d:a] can be used to conduct individual byte write operations. Write operations are qualified by the Write Enable (WE). All writes are simplified with on-chip synchronous self-timed late write circuitry. All operations (Reads, Writes, and Deselects) are pipelined. Pipelined Read Accesses A read access is initiated when the following conditions are satisfied at clock rise: (1) Chip Enable (CE) is asserted active and (2) the Write Enable input signal (WE) is asserted HIGH. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 2.0 ns (250-MHz device) provided OE is active LOW. After the first clock of the read access the output buffers are controlled by OE and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will tri-state following the next clock rise. Bypass Read Operation Bypass read operation occurs when the last write operation is followed by a read operation where write and read addresses are identical. The data outputs are provided from the data in registers rather than the memory array. This operation occurs on a byte to byte basis. If only one byte is written during a write operation and a read operation is performed on the same address; then a partial bypass read operation is performed since the new byte data will be from the datain registers while the remaining bytes are from the memory array. Late Write Accesses The Late Write feature allows for the write data to be presented one cycle later after the access is started. This feature eliminates one bus-turnaround cycle which is necessary when going from a read to a write in an ordinary pipelined Synchronous Burst SRAM. Write access is initiated when the following conditions are satisfied at clock rise: (1) CE is asserted active and (2) the write signal WE is asserted LOW. The address presented to Document No: 001-07844 Rev. *A
CY7C1330AV25 CY7C1332AV25
Ax is loaded into the Address Register. The write signals are latched into the Control Logic block. The data lines are automatically tri-stated regardless of the state of the OE input signal when a write is detected. This allows the external logic to present the data on DQ and DQP (DQ[a:b] for CY7C1332AV25 and DQ[a:d] for CY7C1330AV25). In addition, the address for the subsequent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted). On the next clock rise the data presented to DQ (or a subset for byte write operations, see Write Cycle Description table for details) inputs is latched into the device and the write is complete. The data written during the Write operation is controlled by BWS (BWS[a:d] for CY7C1330AV25 and BWS[a:b] for CY7C1332AV25) signals. The CY7C1330AV25 and CY7C1332AV25 provide byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE) with the selected Byte Write Select (BWS) input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A Synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations. Because the CY7C1330AV25/CY7C1332AV25 is a common I/O device, data should not be driven into the device while the outputs are active. The Output Enable (OE) can be deasserted HIGH before presenting data to the DQ inputs. Doing so will tri-state the output drivers. As a safety precaution, DQ is automatically tri-stated during the data portion of a write cycle, regardless of the state of OE. Power-up/Power-down Supply Voltage Sequencing The power-up and power-down supply voltage application recommendations are as follows: Power-up: VSS, VDD, VDDQ, VREF, VIN. Power-down: VIN, VREF, VDDQ, VDD, VSS. VDDQ can be applied/removed simultaneously with VDD as long as VDDQ does not exceed VDD by more than 0.5V. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the SRAM and VSS to allow the SRAM to adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM, The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is between 175 and 350, with VDDQ=1.5V. The output impedance is adjusted every 1024 cycles to adjust for drifts in supply voltage and temperature.The output buffers can also be programmed in a minimum impedance configuration by connecting ZQ to VDD.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation Page 4 of 19
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PRELIMINARY
guaranteed. The device must be deselected prior to entering the "sleep" mode. CE must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
CY7C1330AV25 CY7C1332AV25
Cycle Description Truth Table[1, 2, 3, 4, 5]
Operation Address Used CE Deselected External Begin Read External Begin Write External Sleep Mode 1 0 0 X WE BWSx CLK ZZ X 1 0 X X X Valid X L-H L-H L-H X 0 0 0 1 Comments I/Os tri-state following next recognized clock. Address latched. Data driven out on the next rising edge of the clock. Address latched, data presented to the SRAM on the next rising edge of the clock. Power down mode.
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC Description Snooze mode standby current Device operation to ZZ ZZ recovery time Test Conditions ZZ > VIH ZZ > VIH ZZ < VIL 2tCYC Min. Max. 128 2tCYC Unit mA ns ns
Write Cycle Descriptions[1, 2]
Function (CY7C1330AV25) Read Write Byte 0 - DQa Write Byte 1 - DQb Write Bytes 1, 0 Write Byte 2 - DQc Write Bytes 2, 0 Write Bytes 2, 1 Write Bytes 2, 1, 0 Write Byte 3 - DQd Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes 3, 1, 0 Write Bytes 3, 2 Write Bytes 3, 2, 0 Write Bytes 3, 2, 1 Write All Bytes Abort Write All Bytes WE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BWd X 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 BWc X 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 BWb X 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 BWa X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Write Cycle Descriptions[1, 2]
Function (CY7C1332AV25) Read Write Byte 0 - DQa Write Byte 1 - DQb Write All Bytes Abort Write All Bytes WE 1 0 0 0 0 BWb X 1 0 0 1 BWa X 0 1 0 1
Notes: 1. X = "Don't Care," 1 = Logic HIGH, 0 = Logic LOW. BWSx = 0 signifies at least one Byte Write Select is active, BWSx = Valid signifies that the desired byte write selects are asserted, see Write Cycle Description table for details. 2. Write is defined by WE and BWSx. See Write Cycle Description table for details. 3. The DQ pins are controlled by the current cycle and the OE signal. 4. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE. 5. OE assumed LOW.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
These SRAMs incorporate a serial boundary scan test access port (TAP) in the FBGA package. This port operates in accordance with IEEE Standard 1149.1-1900 but does not have the set of functions required for full 1149.1 compliance. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test Access Port--Test Clock The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. Test Mode Select The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) on any register. Test Data-Out (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine (see Instruction codes). The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. Performing a TAP Reset A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a high-Z state. TAP Registers Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded into the TDI pin on the rising edge of TCK. Data is output on the TDO pin on the falling edge of TCK. Instruction Register
CY7C1330AV25 CY7C1332AV25
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO pins as shown in TAP Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board level serial test path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between TDI and TDO pins. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all of the input and output pins on the SRAM. Several no connect (NC) pins are also included in the scan register to reserve pins for higher density devices. The boundary scan register is loaded with the contents of the RAM Input and Output ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO pins when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the Input and Output ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Code table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO pins. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
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EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO pins and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because
CY7C1330AV25 CY7C1332AV25
there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
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TAP Controller State Diagram[6] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1
Note: 6. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
CY7C1330AV25 CY7C1332AV25
1
1 SELECT IR-SCAN 0 1 CAPTURE-IR 0
0
SHIFT-IR 1
0
1
EXIT1-IR 0
1
0
PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0
0
0
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TAP Controller Block Diagram 0 Bypass Register TDI Selection Circuitry 31 30 29 . . 2 Instruction Register 2 1 0 1 0
CY7C1330AV25 CY7C1332AV25
Selection Circuitry
TDO
Identification Register 106 . . . . 2 1 0
Boundary Scan Register
TCK TMS
TAP Controller
TAP Electrical Characteristics Over the Operating Range[7, 8, 9]
Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input and Output Load Current GND VI VDD Test Conditions IOH = -2.0 mA IOH = -100 A IOL = 2.0 mA IOL = 100 A 1.7 -0.3 -5 Min. 1.7 2.1 0.7 0.2 VDD + 0.3 0.7 5 Max. Unit V V V V V V A
TAP AC Switching Characteristics Over the Operating Range [10, 11]
Parameter tTCYC tTF tTH tTL Set-up Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise 5 5 ns ns TMS Set-up to TCK Clock Rise TDI Set-up to TCK Clock Rise Capture Set-up to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH TCK Clock LOW 20 20 Description Min. 50 20 Max. Unit ns MHz ns ns
Notes: 7. Minimum voltage equals -2.0V for pulse durations of less than 20 ns. 8. Input waveform should have a slew rate of > 1 V/ns. 9. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table. 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test conditions. tR/tF = 1 ns.
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TAP AC Switching Characteristics Over the Operating Range (continued)[10, 11]
Parameter tCH Output Times tTDOV tTDOX TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 Capture Hold after Clock Rise Description
CY7C1330AV25 CY7C1332AV25
Min. 5
Max.
Unit ns
10
ns ns
TAP Timing and Test Conditions[11]
1.25V 2.5V 50 TDO Z0 = 50 CL = 20 pF 1.25V 0V ALL INPUT PULSES
GND
(a)
tTH
tTL
Test Clock TCK
tTMSS tTMSH
tTCYC
Test Mode Select TMS
tTDIS tTDIH
Test Data-In TDI Test Data-Out TDO
tTDOV tTDOX
Identification Register Definitions
Value Instruction Field Revision Number (31:29) Cypress Device ID (28:12) Cypress JEDEC ID (11:1) ID Register Presence (0) CY7C1330AV25 000 CY7C1332AV25 000 Version number. Description
01011110101100101 01011110101010101 Defines the type of SRAM. 00000110100 1 00000110100 1 Allows unique identification of SRAM vendor. Indicates the presence of an ID register.
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Scan Register Sizes
Register Name Instruction Bypass ID Boundary Scan Bit Size--CY7C1330AV25 3 1 32 70
CY7C1330AV25 CY7C1332AV25
Bit Size--CY7C1332AV25 3 1 32 51
Instruction Codes
Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures the Input/Output ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operation. Captures the Input/Output contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the Input/Output ring contents. Places the boundary scan register between TDI and TDO. Does not affect the SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operation.
Boundary Scan Order (1 Mbit x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Bump ID 5R 6T 4P 6R 5T 7T 7P 6N 6L 7K 5L 4L 4K 4F 6H 7G 6F Bit # 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Bump ID 7E 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 1D 2E 2G Bit # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Bump ID 1H 3G 4D 4E 4G 4H 4M 2K 1L 2M 1N 2P 3T 2R 4N 2T 3R
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Boundary Scan Order (512K x 36)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Bump ID 5R 4P 4T 6R 5T 7T 6P 7P 6N 7N 6M 6L 7L 6K 7K 5L 4L 4K 4F 5G 7H 6H 7G 6G Bit # 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Bump ID 6F 7E 6E 7D 6D 6A 6C 5C 5A 6B 5B 3B 2B 3A 3C 2C 2A 2D 1D 2E 1E 2F 2G 1G Bit # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
CY7C1330AV25 CY7C1332AV25
Bump ID 2H 1H 3G 4D 4E 4G 4H 4M 3L 1K 2K 1L 2L 2M 1N 2N 1P 2P 3T 2R 4N 3R
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied........................................... -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +2.9V Supply Voltage on VDDQ Relative to GND ...... -0.5V to +VDD DC Voltage Applied to Outputs in High-Z State[7] ................................. -0.5V to VDDQ + 0.5V Range Com'l
CY7C1330AV25 CY7C1332AV25
DC Input Voltage[7] ................................ -0.5V to VDD + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... > 1500V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA
Operating Range
Ambient Temperature 0C to +70C VDD 2.37V to 2.63V VDDQ 1.4V to 1.9V
Electrical Characteristics Over the Operating Range
DC Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VIH VIL IX IOZ VREF VIN-CLK VDIF-CLK VCM-CLK IDD ISB1 Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage[12] Output LOW Voltage[13] Output HIGH Voltage Output LOW Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[7] GND VI VDDQ GND VI VDDQ, Output Disabled Typical value = 0.75V Input Leakage Current Output Leakage Current Input Reference Voltage Clock Input Reference Voltage Clock Input Differential Voltage Clock Common Mode Voltage VDD Operating Supply Automatic CE Power-Down Current--TTL Inputs Typical Value =0.75V VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC Max. VDD, Device Deselected, VIN > VIH or VIN < VIL f = fMAX = 1/tCYC 250 MHz 200 MHz 250 MHz 200 MHz Programmable Impedance Mode[14] Programmable Impedance Mode[14] IOH = -0.1 mA, Minimum Impedance Mode[15] IOL = 0.1 mA, Minimum Impedance Mode[15] IOH = -6.0 mA, Minimum Impedance Mode[15] IOL = 6.0 mA, Minimum Impedance Mode[15] Test Conditions Min. 2.37 1.4 VDDQ/2 VSS VDDQ - 0.2 VSS VDDQ - 0.4 VSS VREF + 0.1 -0.3 -1 -1 0.68 -0.3 0.1 0.55 Max. 2.63 1.9 VDD VDDQ/2 VDDQ 0.2 VDDQ 0.4 VDDQ + 0.3 VREF - 0.1 1 1 0.95 VDDQ + 0.3 VDDQ + 0.3 0.95 600 550 280 260 Unit V V V V V V V V V V mA mA V V V V mA mA mA mA
AC Electrical Characteristics Over the Operating Range Parameter VIH VIL Description Input HIGH Voltage Input LOW Voltage Test Conditions Min. VREF + 0.2 - Max. - VREF - 0.2 Unit V V
Notes: 12. IOH = (VDDQ/2)/(RQ/5)+15% for 175 < RQ < 350. 13. IOL = (VDDQ/2)/(RQ/5)+15% for 175 < RQ < 350. 14. Programmable Impedance Output Buffer Mode. The ZQ pin is connected to VSS through RQ. 15. Minimum Impedance Output Buffer Mode: The ZQ pin is connected directly to VSS or VDD. 16. TPower-up: Assumes a linear ramp from 0V to VDD (min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
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Capacitance[17]
Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V VDDQ = 1.5V
CY7C1330AV25 CY7C1332AV25
Max. 5 6 7
Unit pF pF pF
Thermal Resistance[17]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board BGA Typ. 19.7 6.0 Unit C/W C/W
AC Test Loads and Waveforms
VREF = 0.75V VREF OUTPUT Device Under Test Z0 = 50 RL = 50 VREF = 0.75V 0.75V VREF OUTPUT Device Under Test ZQ 5 pF 0.25V Slew Rate = 2 V/ns 0.75V R = 50 ALL INPUT PULSES 1.25V 0.75V
[18]
ZQ
RQ = 250
(a)
RQ = 250 (b)
Notes: 17. Tested initially and after any design or process change that may affect these parameters. 18. Unless otherwise noted, test conditions assume signal transition time of 2 V/ns, timing reference levels of 0.75V, VREF = 0.75V, RQ = 250, VDDQ = 1.5V, input pulse levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of AC Test Loads.
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Switching Characteristics[18, 19, 20, 21]
250 Parameter tPower Clock tCYC FMAX tCH tCL Output Times tCO tEOV tDOH tCHZ tCLZ tEOHZ tEOLZ Set-Up Times tAS tDS tWES tCES Hold Times tAH tDH tWEH tCEH Address Hold After CLK Rise Data Input Hold After CLK Rise WE, BWx Hold After CLK Rise Chip Select Hold After CLK Rise 0.6 0.6 0.6 0.6 Address Set-Up Before CLK Rise Data Input Set-Up Before CLK Rise WE, BWSx Set-Up Before CLK Rise Chip Select Set-Up 0.3 0.3 0.3 0.3 Data Output Valid After CLK Rise OE LOW to Output Clock to Valid[17, 19, 21] 0.5 2.0 0.5 2.0 0.5 Data Output Hold After CLK Rise High-Z[17, 18, 19, 20, 21] Clock to Low-Z[17, 18, 19, 20, 21] OE HIGH to Output High-Z[18, 19, 21] OE LOW to Output Low-Z[18, 19, 21] 2.0 2.0 Clock Cycle Time Maximum Operating Frequency Clock HIGH Clock LOW 1.5 1.5 4.0 250 Description VCC (typical) to the First Access Read or Write
[22]
CY7C1330AV25 CY7C1332AV25
200 Max. Min. 1 5.0 200 1.5 1.5 2.25 2.25 0.5 2.25 0.5 2.25 0.5 0.3 0.3 0.3 0.3 0.6 0.6 0.6 0.6 Max. Unit ms ns MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Min. 1
Notes: 19. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 100 mV from steady-state voltage. 20. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions. 21. This parameter is sampled and not 100% tested. 22. This part has a voltage regulator that steps down the voltage internally; tPower is the time power needs to be supplied above VDD minimum initially before a read or write operation can be initiated.
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Switching Waveforms
READ/WRITE/DESELECT Sequence (OE Controlled)[23, 24, 25, 26]
DESELECT DESELECT WRITE
CY7C1330AV25 CY7C1332AV25
READ
K
tAS tAH tCH tCL
RA3
tCYC
ADDRESS
RA1
WA2
WA5
RA6
WA7
WA8
WE
tWES tWEH
BWSx
tWES tWEH OE/ tEOHZ tDS tDH D2 In tEOLZ tEOV tDOH Q3 Out D5 In tEOHZ Q6 Out D7 In tDH tDS = DON'T CARE = UNDEFINED D8 In
tCLZ
tDOH Q1 Out
Data In/Out
Device originally deselected tCO
tCHZ
Notes: 23. The combination of WE and BWSx (x = a, b, c, d for x36 and x = a, b for x18) define a write cycle (see Write Cycle Description table). 24. All chip enables need to be active in order to select the device. Any chip enable can deselect the device. 25. RAx stands for Read Address X, WAx Write Address X, Dx stands for Data-in for location X, Qx stands for Data-out for location X. 26. CE held LOW.
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DESELECT
WRITE
WRITE
WRITE
READ
READ
READ
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PRELIMINARY
Switching Waveforms (continued)
READ/WRITE/DESELECT Sequence (CE Controlled)
DESELECT DESELECT WRITE
CY7C1330AV25 CY7C1332AV25
Deselect
READ
CLK
tCEH tCH tCL tCYC
tCES
CE
tAS tAH
ADDRESS
RA1
WA2
RA3
WA5
RA6
WA7
WA8
WE
tWES tWEH
BWSx
tWES tWEH tDS tDH tDOH Q1 Out Device originally deselected tCO tCHZ D2 In tDOH Q3 Out D5 In Q6 Out D7 In D8 In
tCLZ
Data In/Out
= DON'T CARE
= UNDEFINED
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DESELECT
WRITE
WRITE
WRITE
READ
READ
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Ordering Information
CY7C1330AV25 CY7C1332AV25
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1330AV25-250BGC CY7C1332AV25-250BGC Package Diagram Package Type Operating Range Commercial
51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1330AV25-250BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1332AV25-250BGXC 200 CY7C1330AV25-200BGC CY7C1332AV25-200BGC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm)
CY7C1330AV25-200BGXC 51-85115 119-ball Fine-Pitch Ball Grid Array (14 x 22 x 2.4 mm) Lead-Free CY7C1332AV25-200BGXC
Package Diagram
119-ball PBGA (14 x 22 x 2.4 mm) (51-85115)
51-85115-*B
All product and company names mentioned in this document are trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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Document History Page
Document Title: CY7C1330AV25/CY7C1332AV25 18-Mbit (512K x 36/1Mbit x 18) Pipelined Register-Register Late Write SRAM Document Number: 001-07844 REV. ** *A Orig. of ECN No. Issue Date Change 469811 503690 See ECN See ECN NXR VKN New data sheet Minor change: Moved data sheet to web Description of Change
CY7C1330AV25 CY7C1332AV25
Document No: 001-07844 Rev. *A
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